刘磊 (Liu, Lei), Ph.D., Associate Professor - ICT, CAS

中国科学院 计算技术研究所 计算机体系结构国家重点实验室 (SKL,ICT,CAS) The Head of Sys-Inventor Research Group, PI Research Interests:Computer ArchitectureMemory System Design and OptimizationOS Design

I received my Ph.D. (Advisor: Prof. Chengyong Wu and Xiaobing Feng) in Computer Science at ICT, where I lead Sys-Inventor Research Group and work with members to improve the performance of computer systems. You can contact me by E-MAIL: LIULEI2010-AT-ICT.AC.CN; LEI.LIU-AT-ZOHO.COM

Lei Liu received the Ph.D. (his Ph.D. thesis, supervised by Wu and Feng) in Advanced Compilation Technology Lab. in State Key Laboratory of Computer Architecture (SKL), Institute of Computing Technology (ICT), Chinese Academy of Science (CAS). During this period, he led (PI, till now) the Sys-Inventor research group and designed the research BPM, BPM+ (DRAM Bank/Channel Partitioning Mechanism in PACT'12 and TACO'14), and Hierarchically Optimizing Data Placement across Cache and Main Memory Banks (ISCA'14). Besides, he received his MS degree in software system design at University of Science and Technology of China (USTC), and BS degree in computer science and engineering at Dalian University of Technology (DLUT). Before he joined ICT, he spent 5 years in industry as a software engineer and senior software architect. He is a visiting scholar in CS at University of Rochester from May/2017 ~ April/2018.

His research field includes computer architecture, memory system design and optimization, and OS design (more details can be found below). As the leading author, his studies are published in ISCA, PACT, IEEE TC (feature paper invited), and ACM TACO, etc. He serves on the Program Committee of IISWC, PACT, ICS, ICPP, ISCA, ASPLOS, IPDPS, HPCC and etc. He is the General co-Chair of ICS-2018.

Now, his team (in SKL, ICT) is looking for creative, self-motivated, hardworking, and resilient students and interns who are interested in computer architecture, system software (e.g., operating systems, languages, compilers). His topic is opened to the scholars who share the similar interests.  


刘磊,男,1981年9月出生于新疆乌鲁木齐市,祖籍辽宁沈阳,现任中科院计算所国重副研究员(Sys-Inventor研究组负责人),硕士生导师。刘磊分别于大连理工大学、中国科学技术大学、中国科学院大学(中科院计算所)获得计算机科学与技术工学学士学位(导师:牛纪桢)、软件系统设计工程硕士学位(导师:赵振西)和计算机体系结构工学博士学位(导师:吴承勇、冯晓兵; 博士论文链接),并于2014年留计算所工作。在进入计算所之前,刘磊在工业界有5年的软件工程师、架构师及项目管理经验。刘磊于2017年5月~2018年4月在美国罗彻斯特大学计算机科学系交流访问。

刘磊的研究领域包括现代操作系统、新型内存系统、体系结构及可扩展性、系统性能评测等多个方面。自2011年起,刘磊带领其课题组在面向多核平台的操作系统、内存资源的利用率、访存优化机制等方向开展了一系列研究,并主导研发了面向主流多核、多通道服务器,及异构存储体系的内存资源管理系统原型。刘磊的研究成果以第一作者并通讯作者发表于ISCA,PACT,IEEE TC,ACM TACO,ICCD等领域内权威学术会议和刊物,并在业内产生了影响力。刘磊曾参与或主持多项国家级项目(包括863、973、自然科学基金青年项目等),此外,他还担任了若干国际学术会议的程序委员会委员、外部评审委员、组委会成员,及学术期刊的审稿人,曾获得 “中国科学院院长优秀奖”、“国家奖学金”、“国科大优秀毕业生”、“计算所优秀科研人员” 等荣誉。


  • Computer System, Memory Architecture, Memory Management and Optimization

  • Operating System, OS for Emerging Technologies and Applications

  • Near Memory Computing, and NVM Technologies

  • Architectural Interaction and Resource Scheduling

  • Profiling and Performance Evaluation

The Sys-Inventor Group (SIG) is engaging in developing state-of-the-art technologies in the field of the operating system, programming model as well as architecture for emerging high-performance computing and systems. At present, our topic is "OS Support for Memory Systems". Here are some of our ongoing project. Contact me, if you are interested in my work or need help.

1. Hybrid Memory Management in OS

The emerging hybrid DRAM-NVM architecture is challenging the existing memory management mechanism in operating systems. In this project, we introduce Memos, which can hierarchically schedule memory resources over the entire memory hierarchy including cache, channels, main memory comprising DRAM and NVM simultaneously. Powered by our newly designed kernel-level monitoring module (HyMM) and page migration engine, Memos can dynamically optimize the data placement at the memory hierarchy in response to the on-line memory patterns, current resource utilization and memory medium features. Our experimental results show that Memos can achieve high memory utilization, improving system throughput by 20~30%. Moreover, Memos can reduce the NVM side memory latency by19~79.5%, energy consumption by 77.8%, and improve the NVM lifetime significantly (40X improvement on average). Our first step effort is in ICCD-2016. The further work is now available in arXiv.

2. Sysmon (2014~Now)

A light-weight OS-level system monitoring tool suite, which is able to profile the memory utilization (including cache utilization, memory footprint, approximate row-buffer locality, physical page level logic re-use time, access frequency, hot/cold features and write/read patterns) without any hardware supports. SysMon is especially useful in VM and system-level research work. Sysmon is now open source on Github. The beta version is introduced in ISCA-2014, TC-2016, and we further discuss reducing the sampling overhead in APPT-2017 in detail.

3. Hierarchically Optimizting Data Placement across Cache and Memory Banks (2013~Now)

To provide ideal overall system throughput and QoS, in this project, the "Vertical Partitioning" is proposed to cooperatively optimize the data placement across cache and DRAM banks. We redesign the memory management component is OS kernel (e.g. buddy system) according to memory architecture details, thus "Vertical Partitioning" can simultaneously mitigate/eliminate the memory interferences at the entire memory hierarchy (i.e. cache-bank). Moreover, we further devise the "Curve-Vertical" Partitioning approach to handle the diverse memory behaviors exhibited by the appearing "memory-diversity" workloads on multi-core platforms. The efforts are published in ISCA-2014 and IEEE TC-2016 (Featured article invited).

4. Reducing Memory Conflicts: DRAM Bank/Channel Partitioning Mechanism (BPM/BPM+) on Real Systems (2011~Now)

This work begins with the contention and interference issue in main memory systems, and I approach it from the Operating System angle. In existing OS, memory resources are "blindly" allocated to applications (threads), leading to memory contentions in DRAM Banks in the root. In order to solve this problem, I extend the well-known Page-Coloring to eliminate/mitigate the interferences between threads on memory banks and channels. These studies help and motivate many works on improving the overall system throughput, locality and QoS. More details are in PACT-2012 and ACM TACO-2014.

SIG: We are glad to see these efforts from Sys-Inventors have had impact on scientific community and industry.


ICT: Lei Liu, Mingjie Xing (2011~2017), Zehan Cui (2011~2012), Chenyong Wu (2010~2014), Yong Li (2013~2015).

Students: Hao Yang, Mengyao Xie, Hongna Geng and Qian Liang.


NSFC under grant No. 61502452 (PI: Lei Liu).

Innovation research project support, SKL (PI: Lei Liu).

863 Program under grant No.2012AA010902 (PI: Xiaobing Feng).

973 Program under grant No.2011CB302504 (PI: Chengyong Wu).

  1. Tackling Diversity and Heterogeneity by Vertical Memory Management

    Lei Liu. arXiv:1704.01198:2017

  2. Memos: Revisiting Hybrid Memory Management in Modern Operating System

    Lei Liu *, Mengyao Xie and Hao Yang. arXiv:1703.07725:2017

  3. SysMon: Monitoring Memory Behaviors via OS Approach

    Mengyao Xie, Lei Liu *, Hao Yang, Chenggang Wu, Hongna Geng. The 12th Intl. Symp. on Adv. Par. Processing Tech. (APPT):2017

  4. Memos: A Full Hierarchy Hybrid Memory Management Framework (Short Paper)

    Lei Liu *, Hao Yang, Yong Li, Mengyao Xie, Lian Li, Chenggang Wu. The 34th International Conf. on Computer Design (ICCD):2016

  5. Rethinking Memory Management in Modern Operating System: Horizontal, Vertical or Random?

    Lei Liu *, Yong Li, Chen Ding, Hao Yang, Chengyong Wu. IEEE Transactions on Computers (TC):2016

    SIG: Trans. Version of the ISCA-2014 paper. This article was a featured article candidate in IEEE TC.

  6. Going Vertical in Memory Management

    Lei Liu *, et al. ACM SIGARCH Computer Architecture News:October, 2014

  7. Going Vertical in Memory Management: Handling Multiplicity by Multi-policy

    Lei Liu *, Yong Li, Zehan Cui, Chengyong Wu. The 41st ACM/IEEE International Symposium on Computer Architecture (ISCA):2014 (acceptance rate: 17.8%)

    SIG: The 9th ISCA paper in mainland China history.

  8. BPM/BPM+: Software-based Dynamic Memory Partitioning Mechanisms for Mitigating DRAM Bank-/Channel-level Interferences in Multicore Systems

    Lei Liu *, Zehan Cui, Yong Li, Chengyong Wu. ACM Trans. on Architecture and Code Optimization (TACO):2014

  9. A Software Memory Partition Approach for Eliminating Bank-level Interference in Multicore Systems

    Lei Liu *, Zehan Cui, Mingjie Xing, Chengyong Wu. The 21st ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT):2012 (acceptance rate: 18.8%)

    SIG: Influential Article in Semantic Scholar -- Cited Greater than 100 Times.

  10. WiseThrottling: A New Asynchronous Task Scheduler for Mitigating I/O Bottleneck in Large-Scale Datacenter Servers

    Fang Lv *, Lei Liu, Huimin Cui, Lei Wang, Ying Liu, Xiaobing Feng, P.C. Yew (UMN). J. of Supercomputing:2015

  11. Dynamic I/O-Aware Scheduling for Batch-Mode Applications on Chip Multiprocessor Systems of Cluster Platforms

    Fang Lv *, Huimin Cui, Lei Wang, Lei Liu, Cheng-Gang Wu, Xiao-Bing Feng, and Pen-Chung Yew (UMN). JCST:2014

    Google Citation, * corresponding author

1.    Memory Resource Optimization Method and Apparatus (PCT, US). First Inventor (with Wu and Feng).

2.    一种存储器资源优化方法和装置 (Chinese Version). First Inventor (with Wu and Feng). 发明人:刘磊、吴承勇、冯晓兵.

SIG: Part of the ideas in ISCA-2014 is within.

  1. 多核系统内存资源管理优化技术的研究(刘磊的博士学位论文,导师:吴承勇、冯晓兵;涵盖本人发表在ISCA,PACT,TACO的成果; Lei's Ph. D. dissertation in Chinese, covering his work in ISCA, PACT and TACO. Supervisor: Wu and Feng)出版物链接

    Defense Committee (May/2014): Fengbin Qi (漆锋斌), Zhaoqing Zhang (张兆庆), Zifeng Hou (侯紫峰), Zhiyong Liu (刘志勇), Wenguang Chen (陈文光), Zhimin Tang (唐志敏), Xiaobin Feng (冯晓兵), Xiaodong Zhang (张晓东)

  2. 编译技术的领路人-谨祝国重编译组张兆庆研究员获得“夏培肃奖”(Invited Essay in Chinese)

  3. PACT-2015 PC会议记录与硅谷工业界访问之行(Invited Essay in Chinese)

  4. ISCA-2014与北美学术之旅(Invited Essay in Chinese)

  5. Page Coloring的历史与发展(Invited Survey in Chinese)

  • Hope you could submit your excellent work to ICS-2018! Here is the CFP. Here is the Call for Workshop.

  • A paper is accepted in APPT-2017.

  • I am now visiting the CS department at U. of Rochester. 罗切斯特大学 的图像结果

  • ICS-2017 will be hold in Chicago. You are expected to submit your excellent work. Hope to see you there.:)

  • Lei Liu is promoted (1/33,14/15). Thank all of my friends. :)

  • A paper is accpeted in ICCD-2016, to appear at the conference in Phoenix, AZ, US.

  • [Good News]: ICS-2018 will be hold in Beijing, hosted by SKL, ICT, organized by Lei Liu, Michael Gschwind, Avi Mendelson, P-C Yew and Xiaobing Feng, etc. Come and join us, and let us make ICS a great success in China!

  • I will go to attend ICS-2016 from 1/June to 3, in Istanbul, and bid for ICS-2018, Beijing. Good Luck for all of our colleagues!

  • Best Wishes to all of my friends and collaborators! I wish you a very happy and fruitful new year, 2016, way to go!

  • Happy Teachers' Day (教师节快乐) on 10/9/2015! I would like to extend my deep thanks to Prof. Zhang, Wu and Feng for their help in my Ph.D., and on behalf of professors in compiler team, I would like to extend our thanks to all of the students! You are the pride of us! Stay hungry, Stay foolish.

  • Our research entitled "An Investigation into Asymmetry Multi-Channel Architecture for Supporting Heterogeneous Memory System and the Corresponding Heuristic Memory Management Mechanism" will be supported by a new funding from Natural Science Foundation (NSF) of China from 2016 to the end of 2018. Congratulations to Sys-Inventors!

  • I am visiting VMware (CA,US) and Huawei research center (CA,US) from 27/July ~ 3/Aug 2015. The theme is "Rethinking Memory Management in Modern Operating System -- Memory Optimization by Leveraging Hardware Features".

  • Congratulations! The paper entitled "Rethinking Memory Management in Modern Operating System" from our Sys-Inventor group in Compiler team is Accepted by IEEE Trans. on Computers! Thank all of the authors for their contributions. On behalf of the authors in this paper, I would like to extend my deep thanks to these who pay attentions on our work for their valuable comments, especially Prof. Xiaodong Zhang (Ohio), P. C. Yew (UMN). This is a further step of our work in ISCA-2014, and more details of new findings are presented in this paper. You are expected to read it.

  • Hao Yang and Mengyao Xie joined us. Welcome!

  • I am visiting VMware in Palo Alto. CA US. (will give a talk about system optimization on 23 June 2014, Monday).  

  • I go now to attend ISCA-2014 in MN US., and will present "Going Vertical in Memory Management" on 16 June Monday.

  • Congratulations! The paper "Going Vertical in Memory Management: Handling Multiplicity by Multi-policy" from our Sys-Inventor group in Compiler team was accepted by ISCA-2014.

  • Congratulations! The further work on DRAM Bank partitioning from Sys-Inventor, BPM/BPM+, was accepted by ACM TACO-2014.

  • Congratulations! The work on DRAM Bank partitioning from Sys-Inventor, was accepted by PACT-2012.

  • 100-Academic-Stars Program, ICT, 2017

  • Outstanding Scientific Researcher (Outstanding Faculty Award), ICT, 2015

  • National Scholarship for Ph.D

  • Chinese Academy of Sciences President's Award for Excellence, Chinese Academy of Sciences

  • Outstanding Graduates, Chinese Academy of Sciences

  • Advanced Individual in State Key Lab. of Computer Architecture, ICT

  • The Bewinner Communications (北纬通信) Second Prize for Self-dependent Innovation

  • Merit student, Chinese Academy of Sciences

  1. Member of the Program Committee of IISWC-2017

  2. Member of the Program Committee of ICPP-2017

  3. Member of the Program Committee of ICS-2017, and Chair of Session 5

  4. General co-Chair (w/ Dr. Michael Gschwind) of ICS-2018, Beijing, China

  5. Member of the Program Committee of PACT-2015, 2016 (ERC)

  6. Member of the External Review Committee of ISCA-2016

  7. Member of the Program Committee of IEEE IPDPS-2016

  8. Member of the Program Committee (ERC) of ASPLOS-2016, 2017, 2018 and Chair of Session Runtimes

  9. Member of the Program Committee of HPCC-2015, 2016

  10. Member of the Program Committee of HP3C-2017, 2018


  12. Review Expert of National Science Foundation of China (NSFC)

I'm fortunate to work or have worked with some of these brilliant ones, and also thank the former participants.

-- Students

  • Mengyao Xie (Ph.D Candidate)

  • Hongna Geng (Ph.D Candidate)

  • Qian Liang (Master Degree Candidate)

  • Shengjie Yang (Graduate)

-- Former Students

  • Hao Yang, Master 2017, Huawei

-- Recent and Former Collaborators

  • Chenliang Xu (Professor, UR)

  • Lingda Li (BNL)

  • P-C Yew (UMN)

  • Mingjie Xing (Engineer, ICT)

  • Lian Li (Professor, ICT)

  • Chenggang Wu (Professor, ICT)

  • Chen Ding (UR)

  • Yong Li (Engineer in VMware. Former collaborator from 2013~2015)

  • Fang Lv (Faculty, ICT)

  • Zehan Cui (Within ICT till 2016. Former collaborator from 2011~2012)

-- Former Member

  • yungang Bao (Former participant from 2011.11~2012 on early step writing work). 注:由于学术、组织等方面的原因,本研究组已于2013年起停止了与部分参与者的非正式合作,不属于本人发表在12/14年论文的主要合作者。论文更正版本已发布,如有疑问,欢迎与本实验室联系

Lei Liu Ph.D, 2014, ICT, CAS

Chengyong Wu Ph.D, 2000 and Xiaobing Feng Ph.D, 1999, ICT, CAS

Zhaoqing Zhang 1960, PKU

Address: 北京海淀区科学院南路6号0612J(0612J, No.6 Kexueyuan South Road Zhongguancun,Haidian District Beijing,China)。

Post Code: 100190

Updated on:2018-04-02 12:15      Total Visits:23766


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